M=NORMAL, L=NORMAL, E=DISABLED
Controls operation of the memory controller.
| E | EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1] 0 (DISABLED): Disabled 1 (ENABLED): Enabled. (POR and warm reset value). |
| M | Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed. 0 (NORMAL): Normal. Normal memory map. 1 (RESET): Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value). |
| L | Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1] 0 (NORMAL): Normal. Normal mode (warm reset value). 1 (LOW_POWER_MODE): Low-power mode. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |